1. Field of the Invention
The present invention relates to a time difference amplifier, and more particularly, to a time difference amplifier using slew rate control, in which the slew rates of internal output voltages are changed according to a phase combination of digital input signals such that a time gain is determined by a ratio between the slew rates, thereby allowing the slew rates to be regulated from an outside to control the time gain.
2. Description of the Related Art
These days, with the development of semiconductor processing technologies, the operating speed of an analog integrated circuit has been improved, and the power supply voltage of the analog integrated circuit has been decreased. Under these situations, a characteristic that a time resolution is more excellent than a voltage resolution results. Due to this fact, recently, instead of an analog-to-digital converter (ADC) for converting a voltage difference between analog signals into a digital value, a time-to-digital converter (TDC) tends to be used. By not solely using a time-to-digital converter and instead serially connecting a voltage-controlled delay line (VCDL) with a time-to-digital converter, the voltage-controlled delay line can convert a difference between analog voltages into a time difference between the rising edges of two digital signals, and the time-to-digital converter can convert the time difference into a digital value, so that the same effects as in an analog-to-digital converter can be accomplished.
There are various methods for improving the time resolution of a time-to-digital converter. One of these methods is to use a time difference amplifier by connecting it to the front end of a time-to-digital converter.
The time difference amplifier is a circuit which amplifies a time difference between changing edges of two digital input signals at a predetermined rate and increases a time difference between changing edges of two digital output signals. The time gain of the time difference amplifier is defined as a value acquired by dividing a time difference between the changing edges of two digital output signals by a time difference between the changing edges of two digital input signals.
FIG. 1 is a diagram showing the function of a conventional time difference amplifier. Referring to FIG. 1, when assuming that a time difference between the changing edges of first and second digital input signals IN1 and IN2 inputted to a time difference amplifier 110 is Δ TIN and a time difference between the changing edges of first and second digital output signals OUT1 and OUT2 of the time difference amplifier 110 is Δ TOUT, a time gain G of the time difference amplifier 110 is Δ TOUT/Δ TIN.
As described above, a time difference amplifier is used by being serially connected with a time-to-digital converter, and FIG. 2 shows an example. Referring to FIG. 2, the two output terminals of a time difference amplifier 210 are serially connected to the two input terminals of a time-to-digital converter 220. In this case, since a time difference between the changing edges of two digital signals inputted to the time-to-digital converter 220 are amplified by the time difference amplifier 210, the time resolution of the time-to-digital converter 210 is resultantly improved.
FIG. 3 is a diagram showing a principle that a time resolution is improved in the conventional time difference amplifier. Referring to FIG. 3, when a time difference amplifier with a time gain of G and a time-to-digital converter with a time resolution of Td are connected in series as shown in FIG. 2, a final time resolution becomes Td/G. In this case, a time resolution is improved further while a circuit size and power consumption are significantly decreased, when compared to a method for improving a time resolution of a conventional time-to-digital converter which uses Vernier delay lines where a time delay difference between two delay lines corresponds to a time resolution of the time-to-digital converter.
In order for a time difference amplifier to be effectively used in various application fields, some conditions should be satisfied. Typical conditions include a large gain, a wide input range and linearity.
That is to say, for a time period with a wide time difference between the changing edges of two digital input signals inputted to a time difference amplifier, it is necessary to satisfy conditions that a time difference between the changing edges of two digital output signals is maintained at a constant rate with respect to a time difference between the changing edges of the two digital input signals and the rate has a large value.
The reason to this resides in that, since a time difference amplifier is used by being coupled mainly with a time-to-digital converter as described above, a number of time difference amplifiers should be connected in series when a time gain is small, to obtain a desired time gain and a desired time resolution. Another reason resides in that, in the case where a time difference amplifier operates only in a period with a narrow time difference between the changing edges of input signals, the operating range of the time-to-digital converter is limited. Still another reason resides in that, in the case where a time gain of a time difference amplifier is not constant with respect to the time difference between the changing edges of the input signals, the time difference amplifier cannot be used in an application where a precise time period is to be measured.
FIG. 4 is a circuit diagram of a conventional time difference amplifier. Referring to FIG. 4, a conventional time difference amplifier 400 has a positive feedback loop structure. Here, the time difference amplifier 400 is a time difference amplifier which uses the metastable phase of SR latches 410 and 420. In other words, the time difference amplifier 400 is a time difference amplifier which uses a phenomenon that a time required for phase change of two output signals is lengthened as a time difference between the changing edges of two digital input signals is shortened. The time difference amplifying function of the time difference amplifier 400 is performed only when the time difference between the changing edges of two input signals falls in a period with a metastable phase. Moreover, in the time difference amplifier 400, since the value of a time gain is not constant with respect to the time difference between the changing edges of the input signals, the time difference amplifier 400 may be used only during a substantially narrow time period (of ±40 ps). Furthermore, a time gain is limited to 20 at the maximum.
FIG. 5 is a circuit diagram of another conventional time difference amplifier. A time difference amplifier 500 shown in FIG. 5 also has a positive feedback loop structure and includes an SR latch 510 based on NAND gates ND1 and ND2. The time difference amplifier 500 is a time difference amplifier which operates according to a principle that discharge degrees by pull-down circuits of the two NAND gates ND1 and ND2 symmetrically disposed are determined by outputs of opposite-side NAND gates ND1 and ND2 so that the output of one NAND gate of which input phase is changed earlier is changed quickly and the output of the other NAND gate of which input phase is changed later is changed slowly.
The time difference amplifying function of the time difference amplifier 500 is performed only during a narrow input time period such that it is possible to control influence of the respective outputs of the two NAND gates ND1 and ND2 over operations of opposite-side NAND gates ND1 and ND2. Since the time difference amplifier 500 has the positive feedback loop structure, the value of a time gain is not constant with respect to a time difference between the changing edges of input signals, and thus, in order to correct this, a correction unit 520 based on a voltage-controlled delay line (VCDL) is needed. The time gain of the time difference amplifier 500 is locked to 2, and a maximum input time period is about ±100 ps in the case of using the correction unit 520. In order to increase a time gain, a cascade structure in which a number of time difference amplifiers are consecutively connected should be used.
As a consequence, in the conventional time difference amplifier, the value of a time gain is not constant with respect to a time difference between the changing edges of input signals due to the positive feedback loop structure, and thus, problems are caused in that the time difference amplifier may be used only in a very narrow time period and a time gain is small.
Also, in the conventional time difference amplifier, since the cascade structure in which a number of time difference amplifiers are consecutively connected should be used in order to increase a time gain, a large space and a lot of costs are needed.